MAURIN, M Louis (2024) Investigating scheduling mechanism for High Level Synthesis PRE - Research Project, ENSTA.
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Abstract
High-Level Synthesis (HLS) plays a crucial role in bridging the gap between software and hardware design by enabling the automatic generation of hardware circuits from high-level programming languages. This report presents a twofold contribution to the JLM compiler framework. First, it details a solution for converting the Regionalized Value State Dependence Graph (RVSDG) in JLM to and from an MLIR dialect, enhancing interoperability and flexibility in compiler design. Second, the report describes the implementation of statically scheduled HLS within JLM, offering an approach that optimizes both performance and resource utilization. Throughout this project, significant learning was required to address the complex challenges associated with compiler and hardware design, which led to valuable contributions and set the stage for future research in this field.
Item Type: | Thesis (PRE - Research Project) |
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Uncontrolled Keywords: | JLM – Regionalized Value State Dependence Graph (RVSDG) – Multi-Level Intermediate Rep- resentation (MLIR) – Chisel – High-Level Synthesis (HLS) – Static Scheduling |
Subjects: | Information and Communication Sciences and Technologies |
ID Code: | 10149 |
Deposited By: | Louis MAURIN |
Deposited On: | 28 août 2024 11:12 |
Dernière modification: | 28 août 2024 11:12 |
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