École Nationale Supérieure de
Techniques Avancées

Abstract

In this document we present a design space exploration methodology for SOC architectures in telecommunication domain. The significant evolution of semiconductors technology has allowed the implementation of complete systems on a single chip. This implementation was made possible by the design methodologies based on the re-use of existing (IP - Intellectual Property) components in the system. Differentiation of the systems being obtained by the addition of IP owners attached to the system. The traditional technologies based on the Y (Y-charts) and the techniques of Co-design proved to be insufficient as they used non-parameterizable Hard IPs for the system. So, for better dimensioning of the system, Soft IPs were proposed which are parameterizable by nature and hence create a huge design exploration space proving extremely useful and not exploitable by ad hoc technique or interactive design. The problem arising is a mathematical optimization problem of the parameters of the whole of IPs software constituting the SOC. This multidimensional problem in performance is worsened when within the framework of SOC for embedded systems of the severe criteria of energy consumption and silicon surface area are also of equal importance. So the problem becomes a multidimensional problem of multiobjective optimization. This thesis contributes to the resolution of this problem proposing a solution consisting of several stages. In a first stage, the techniques of exploration for the dimensioning of SuperScalar processor IPs are proposed which take account of the three criteria: performance, consumption of energy and silicon surface area. The obtained results on multi-media benchmarks "MiBench" resulted in an optimal subset consisting of Pareto function making it possible to select one or more of the effective solutions for the selected applications. This first stage being realized in the thesis also proposes a second contribution which extends the preceding framework by coupling multi-objective exploration with a physical implementation on FPGA circuits allowing an exploration with physical hardware in the loop. The principle followed is the reverse of explorations carried out has high levels of abstraction (SystemC) is that an exploration is all the more effective since the values injected with the algorithm of exploration are close to reality. The other aspect is that exploration by simulation of the SOC remains problematic due to prohibitory times of simulation and that the direct execution is increasingly faster thus allows broad and realistic explorations. This approach is applied to LEON processor v2.0 "ESA" to Xilinx circuits Virtex-II which from their reconfigurability allow the loading of new configurations during exploration. Lastly, the importance of the mixed analog-digital SOC raised our interest to devise an optimization methodology for the analog circuits based primarily on the same principle. Only difference in this methodology was the usage of FPAA circuits (Field Programmable Analog Array) which allows the design and the implementation of applications on reprogrammable analog circuits. This methodology makes it possible to test and explore many configurations by physically implementing them in a programmable circuit at a lower cost.The thesis concludes with a prospective note on possible future research directions appearing from the contributions of this work on methodologies of SOC design in SOPC environments.