Paillet, F. et Mercier, D. et Bernard UEI/AVA, Thierry et Senn, E. (1999) Low power issues in a digital programmable artificial retina In: Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design, 1999.
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Official URL: http://portal.acm.org/citation.cfm?id=832287.83566...
Programmable Artificial Retina (PAR) means lodging a digital Processing Element in each pixel of a focal plane array. A PAR is faced with constraints coming from the meeting of both optical sensor and processor domain. Image sensing is sensitive to device temperature. Then heat dissipation should be limited. High resolution sensor implies large chip and small pixel area. Combining these characteristics with the power hungry nature of the vision processing task ends the equation to consider. Large array means many processors and potentially power consumption without the usual possibility of trading power against silicon area, due to extreme geometrical constraints. The considerations therein are based on experimenting our last PAR chip fabricated in standard 0.8um CMOS technology, called PVLSAR2.2 (Programmable Versatile Large Size Artificial Retina (pronounced ``pulsar'')), which features a resolution of 128x128 pixels and among others, the ability to operate both under and above threshold voltage. Power considerations are tackled at three levels: power savings from the artificial retina concept at the vision system level, power issues from global architecture of the chip and reducing power consumption in the processing task itself.
|Item Type:||Conference or Workshop Item (Lecture)|
|Subjects:||Information and Communication Sciences and Technologies|
|Deposited By:||Julien Karachehayas|
|Deposited On:||04 févr. 2008 01:20|
|Dernière modification:||05 juin 2013 09:13|
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